This invention relates to an oscillator circuit and, more particularly, to an oscillator circuit adapted to serve as a power supply for an integrated-circuit chip that utilizes complementary metal-oxide-semiconductor (CMOS) technology.
It is known that low-power-dissipation operation of a conventional CMOS circuit can be achieved if the power supply lead of the circuit is ramped repetitively between VDD and VSS. During the so-called power-down phase of each ramped cycle, the state of the circuit is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called PPS (pulsed power supply) CMOS and is characterized by a power dissipation property that is typically approximately an order of magnitude less than that of conventional CMOS. The technique is described in "Pulsed Power Supply--PPS CMOS" by T. J. Gabara, Proceedings of 1994 IEEE Symposium on Low Power Electronics, San Diego, Calif., Oct. 10-12, 1994, pages 98-99. Further, the technique is described in T. J. Gabara's copending commonly assigned U.S. patent application designated Ser. No. 08/225,950, filed Apr. 8, 1994, now U.S. Pat. No. 5,450,027.
In practice, an oscillator circuit designed to generate a sinusoidal waveform can be utilized to power PPS CMOS circuits. Ideally, such an oscillator circuit should be relatively simple and should itself exhibit a relatively low-power-dissipation characteristic.
As the trend grows to miniaturize electronic equipment and to make it more portable, increasing emphasis is being put on trying to devise other ways to reduce the power dissipation of such equipment. Thus, even in equipment utilizing low-power-dissipation PPS CMOS circuits, it is generally advantageous during so-called inactive periods (for example, when no new data signals are being applied to the equipment for extended periods of time) to conserve power by connecting the PPS circuits to a constant-VDD power supply. When so connected, the circuits resemble conventional CMOS circuits in every way. And, importantly, no power (except that stemming from diode leakage currents) is thereby consumed during the inactive periods. Once input data signals resume, the circuits are reconnected to the pulsed (or sine-wave) power supply thereby to enable operation during active periods in the unique low-power-dissipation manner that is characteristic of PPS circuits. Such switching between a pulsed power supply (during active data periods) and a constant-VDD power supply (during inactive data periods) is described in concept in the aforecited application.